The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value.
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机译：块体CMOS技术有望缩小至32nm节点，其后继者可能是FinFET。 FinFET是一种超薄型多栅极MOS晶体管，具有其他特点，与传统的体MOS晶体管相比，其电压增益要高得多[1]。带隙基准电路不能直接从体CMOS技术移植到SOI FinFET技术，因为既不能在薄SOI层中实现传统的二极管，又不能在仅具有金属（lic）栅极的工艺中容易获得面积有效的电阻器。在本文中，采用32nm SOI FinFET技术实现了低于1V的带隙基准电路，该架构显着降低了所需的总电阻值。
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